Flash memory is a commonly used type of non-volatile memory in widespread use as mass storage for consumer electronics, such as digital cameras and portable digital music players for example. The density of a widely available flash memory chip can be up to 4 GB (at present) which is suitable for use in popular USB flash drives since the size of one flash chip is small.
The advent of 8 mega pixel digital cameras and portable digital entertainment devices with music and video capabilities has spurred demand for ultra-high capacities to store the large amounts of data, which cannot be met by the single flash memory device. Therefore, multiple flash memory devices are combined together into a memory system to effectively increase the available storage capacity. For example, flash storage densities of 20 GB may be required for such applications. Higher density systems can be realized for hard disk drive (HDD) applications.
FIG. 1 is a general block diagram of typical flash memory of the prior art. Flash memory 10 includes logic circuitry such as control circuit 12, for controlling various functions of the flash circuits, registers for storing address information, data information and command data information, high voltage circuits for generating the required program and erase voltages, and core memory circuits for accessing the memory array 14. The control circuit 12 includes a command decoder and logic for executing the internal flash operations, such as read, program and erase functions. The functions of the shown circuit blocks of flash memory 10 are well known in the art. Persons skilled in the art will understand that flash memory 10 shown in FIG. 1 represents one possible flash memory configuration amongst many possible configurations.
The memory cell array 14 of the flash memory 10 of FIG. 1 consists of any number of banks, which is a selected design parameter for a particular flash device. FIG. 2 is a schematic illustration showing the organization of one bank 20 of the memory cell array 14 of FIG. 1. Bank 20 is organized into k+1 blocks, and each block consists of i+1 pages. Both k and i are integer values. Each page corresponds to a row of memory cells coupled to a common wordline. A detailed description of the memory cells of the block follows.
Each block consists of NAND memory cell strings, having up to i+1 flash memory cells 22 serially arranged and electrically coupled to each other. Accordingly, wordlines WL0 to WLi are coupled to the gates of each flash memory cell in the memory cell string. A string select device 24 coupled to signal SSL (string select line) selectively connects the memory cell string to a bitline 26, while a ground select device 28 coupled to signal GSL (ground select line) selectively connects the memory cell string to a source line, such as VSS. The string select device 24 and the ground select device 28 are n-channel transistors.
There are j+1 bitlines 26 common to all blocks of bank 20, and each bitline 26 is coupled to one NAND memory cell string in each of blocks [0] to [k]. Variable j is an integer value. Each wordline (WL0 to WLi), SSL and GSL signal is coupled to the same corresponding transistor device in each NAND memory cell string in the block. As those skilled in the art should be aware, data stored in the flash memory cells along one wordline is referred to as a page of data.
Coupled to each bitline outside of the bank 20 is a data register 30 for storing one page of write data to be programmed into one page of flash memory cells. Data register 30 also includes sense circuits for sensing data read from one page of flash memory cells. During programming operations, the data registers perform program verify operations to ensure that the data has been properly programmed into the flash memory cells coupled to the selected wordline. Programming within a block typically starts at the page corresponding to WL0, and proceeds sequentially up to WLi to fill the present block. Alternately, programming can start at WLi and proceed sequentially down to WL0. Then programming continues with WL0 of a new block. Within a device, blocks are typically programmed in sequence.
The flash cells of flash memory 10 can store data in one of two different modes. Data can be stored in a single bit per cell (SBC) storage mode or a multiple bit per cell (MBC) storage mode. In the SBC storage mode, exactly one bit of information is stored in one cell to represent one of two possible states. In the MBC storage mode, two bits are stored in one cell to represent one of four possible states. Of course, three bits or more can be stored in one cell, but the example of having two bits stored in one cell will be used from this point forward. The advantage of storing data in the MBC storage mode (two bits per cell or more) is the at least doubling of storage capacity over the SBC storage mode when using the same number of cells. The main circuits of the flash memory 10 are substantially the same when storing data in the SBC storage mode or the MBC storage mode. Therefore, flash memory manufacturers apply a mask option during the fabrication process to configure the flash memory 10 to execute either SBC specific algorithms or MBC specific algorithms, since the flash circuits are controlled differently between SBC and MBC read and program operations.
FIG. 3 shows a threshold voltage (Vt) distribution graph for erased memory cells and programmed memory cells in the SBC storage mode. Due to process and voltage supply variations, the erased and programmed threshold voltages are distributed within a voltage range. As shown in FIG. 3, erased memory cells have a negative threshold voltage between −3V to −1V, while programmed memory cells have a positive threshold voltage between 1V and 3V. The ranges depend on the desired threshold voltage for the memory cells. The threshold voltage ranges are illustrative of possible threshold voltages that can be used in a particular flash memory device, however those skilled in the art will understand that the selection of threshold voltages to use for erased and programmed memory cells will depend on the design and manufacturing process of the flash memory device. Persons skilled in the art will understand that different flash devices will have different threshold voltage ranges to suit a particular design or application.
FIG. 4 shows a threshold voltage (Vt) distribution graph for erased memory cells and programmed memory cells in the MBC storage mode. Erased memory cells have a negative threshold voltage, and there are three ranges of positive threshold voltages that the memory cell will store, each corresponding to a different state. Preferably, the min and max ranges of threshold voltages for each state should be minimized, while the spacing between the ranges should be maximized.
It is well known that flash memory devices have a limited number of erase-program cycles before they can no longer be used to store data reliably. More specifically, flash memory cells are subject to program/erase cycle wearing, which is a progressive degradation of a flash memory cell due to cumulative program and erase operations. It is noted that a memory block is always erased first prior to being programmed with data, hence the cycles can be referred to as both program and erase cycles. It is the understanding of those skilled in the art that all currently known flash memory is configured for block erase, meaning that if just one page of data in a block is to be modified, the entire block containing that page is erased and re-programmed with the modified page and the unmodified pages. The effect of such cumulative program and erase operations is the alteration of the program and erase characteristics of the memory cell beyond optimal parameters. When memory cells are degraded, higher program and erase voltages are needed to program or erase the memory cells to the desired threshold voltages. Eventually, the memory cells will fail to retain data (i.e. desired threshold voltage) properly. For example, the typical rated erase-program cycles for current SBC flash memory is about 100,000 cycles. However, current MBC flash memory has a smaller rated limit 10,000 cycles. The above mentioned erase-program cycle limits are examples only, but it is well understood that MBC erase-program cycles are lower by a significant factor over SBC erase-program cycles.
Currently, most flash memory available is of the MBC type due to the large storage density relative to its chip size. While this is suitable for most consumer applications, the 10,000 cycle program-erase limit may be insufficient for other applications where data programming and erasing is frequent. Therefore, when an MBC flash memory has reached its 10,000 cycle life span, it is no longer usable and must be discarded. This problem is more critical for commercial applications, such as HDD applications, where there are more frequent program-erase cycles. Because HDD applications require higher data integrity than most consumer applications, MBC flash memory is not suited for use due to its relatively short 10,000 cycle life span.
It is, therefore, desirable to provide a flash memory and flash memory system suitable for both consumer and commercial applications, having an extended life span.